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Opis

This book investigates the architecture design, physical implementation, result evaluation, and feature analysis of a many-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with respect to each other in a Globally Asynchronous Locally Synchronous fashion. The processor is called Asynchronous Array of simple Processors (AsAP). A 6×6 array has been fabricated in a 0.18 µm CMOS technology. The physical design concerns timing issues for robust implementations, and takes full advantages of their potential scalability. Each processor occupies 0.66 mm˛, is fully functional at a clock rate of 520-540 MHz under 1.8 V, and dissipates 94 mW while the clock is 100% active. The system is also easily scalable, and is well- suited to future fabrication technologies.

Szczegóły książki

Kategoria Książki po angielsku Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Pełny tytuł: High Performance and Energy Efficient Many-core DSP Systems An Asynchronous Array of Simple Processors
• Autor: Zhiyi Yu
• Język: Angielski
• Oprawa: Miękka
• Liczba stron: 172
• EAN: 9783639098594
• ISBN: 3639098595
• ID: 06818882
• Wydawca: VDM Verlag
• Waga: 236 g
• Wymiary: 229 × 152 × 9 mm
• Data wydania: 01. December 2008

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