Verification Methodology Manual for SystemVerilog / Najlacnejšie knihy
Verification Methodology Manual for SystemVerilog

Code: 09165363

Verification Methodology Manual for SystemVerilog

by Hunter, Alan (North Carolina State University, University of Leeds North Carolina State Univ. North Carolina State Univ. North Carolina State Univ. No

Offers users the first resource guide that combines both the methodology and basics of SystemVerilog§§Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.§§Unique ... more

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Book synopsis

Offers users the first resource guide that combines both the methodology and basics of SystemVerilog§§Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.§§Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.§

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Book category Books in English Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

132.30

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