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Viac informácií o knihe ASIC Design and Synthesis

• Parametre knihy
• Anotácia kniha
• Obľúbené z iného súdka

Nákupom získate 368 bodov

Anotácia knihy

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Parametre knihy

Zaradenie knihy Książki po angielsku Technology, engineering, agriculture Electronics & communications engineering Electronics engineering

• Celý názov: ASIC Design and Synthesis
• Podnázov: RTL Design Using Verilog
• Autor: Vaibbhav Taraate
• Jazyk: Angličtina
• Väzba: Brožovaná
• Počet strán: 330
• EAN: 9789813346444
• ID: 38574120
• Nakladateľ: Springer Verlag, Singapore
• Hmotnosť: 539 g
• Rozmery: 235 × 155 × 20 mm
• Dátum vydania: 08. January 2022

Obľúbené z iného súdka

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